1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, a method of designing a semiconductor integrated circuit using automatic placement of standard cells, and a device for designing the same.
2. Description of the Prior Art
In recent years, demands for high-speed operation of semiconductor integrated circuits are increasingly being grown. However, the increase in power consumption when inoperative has to be suppressed. A designing method has been known in which high-speed transistors having high switching-speeds and slightly large leakage currents in off state and low-leakage transistors having very small leakage currents in off state and slightly low switching-speeds are used for settling the above demands. A major part of a semiconductor integrated circuit is designed by using low-leakage transistors, and a circuit portion requiring high-speed operation is designed by using high-speed transistors. A high-speed transistor has the same shape as a low-leakage transistor when viewed in a plan view, but has characteristics, e.g., the low absolute value of a threshold voltage, a thin gate insulating film, a short effective channel length, and the like. For the same gate voltage, a larger drain current can be made to flow in the high-speed transistor. Thus, the high-speed transistor has voltage-to-current characteristics different from those of the low-leakage transistor.
On the other hand, as disclosed in, for example, Japanese Unexamined Patent Publication No. Hei 8(1996)-87533, automatic placement and automatic wiring are broadly used in which standard cells are used for making layout design more efficient. The designing method shown in FIG. 1 has been used in the case where a plurality of types of transistors, such as high-speed transistors and low-leakage transistors, having different voltage-to-current characteristics are integrated on one chip using the automatic placement of standard cells.
In FIG. 1, first, in Step 1302, for design using cells of a high-speed type in a timing-critical circuit portion requiring high-speed operation, the entire netlist 1301 is divided into the following modules: a module of a portion where operation timing is critical, for example, for a reason such that a signal has to pass through a large number of stages of gates for one clock, or the like, and a module (top module 1308) of the other portion. Here, a cell of a high-speed type means a cell constituted by high-speed transistors. Hereinafter, a cell of a high-speed type is referred to as a high-speed cell, and a cell constituted by a low-leakage transistor cell is referred to as a low-leakage cell. A high-speed cell library 1305 is a library of high-speed cells, and a low-leakage cell library 1310 is a library of low-leakage cells.
In a placement step 1306, cells are placed based on a netlist of a timing-critical module 1303 using floor plan data 1304, which is data representing a placeable area, and the high-speed cell library 1305. The timing-critical module 1303 in which the placement step has been completed is stored in a timing-critical module library 1307.
In a placement step 1311, the cells are placed based on a netlist of the top module 1308 using floor plan data 1309 and the low-leakage cell library 1310. Moreover, the timing-critical module is placed by using the timing-critical module library 1307, thus creating layout data 1312 for the whole chip. FIG. 2 is a diagram schematically showing cell placement realized by the above designing method.
Incidentally, the timing-critical circuit portion constituted by high-speed cells and the other circuit portion constituted by low-leakage cells need to be placed away from each other by a certain distance. This is because a mask margin is required so that a process (e.g., ion implantation, etching, and the like) specific to transistors of one type may not affect structures and characteristics of transistors of the other type in a diffusion process since high-speed transistors for a high-speed cell and low-leakage transistors for a low-leakage cell are different from each other in terms of structure and characteristics.
Accordingly, in the aforementioned designing method, the outline of each macro constituting the top module becomes a block constituted by a combination of rectangles. Moreover, for improving the placement quality of the top module, a timing-critical circuit (the timing-critical module in FIG. 1) is often placed in the peripheral area of the chip or around another large-scale macro. In the case where the timing-critical circuit portion is placed in the peripheral area of the chip or around another large-scale macro, the wiring lengths of an input signal line and an output signal line are lengthened, and a delay is increased. Therefore, there are many cases where the effect of using the high-speed cell library is impaired.
As described above, in the known designing method, since a high-speed cell macro 1402 (corresponding to the timing-critical module in FIG. 1) constituted by high-speed cells and a low-leakage cell macro 1401 (corresponding to the top module in FIG. 1) constituted by low-leakage cells are respectively placed as individual blocks, the effect of using the high-speed cell library has not been sufficiently exerted.